A Power Gating Switch for Low Power 8 Bit CMOS Full Adder Circuit

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Provided by: International Journal on Emerging Technologies
Topic: Hardware
Format: PDF
In most recent CMOS feature sizes (e.g., 90nm and 45nm); leakage power dissipation has become an overriding concern for VLSI circuit designers. International Technology Roadmap for Semiconductors (ITRS) reports that leakage power dissipation may come to dominate total power consumption. Leakage is mainly due to the scaling of CMOS. There are static and dynamic (switch mode) power losses occurs in CMOS circuit, in which static power is more important for sleep mode (no operation mode), leakage reduction improves the efficiency of the circuit, thereby saving a significant amount of energy.
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