A Proficient Design of Hybrid Synchronous and Asynchronous Digital FIR Filter Using FPGA

In this paper, a hybrid synchronous and asynchronous digital FIR filter is designed and implemented in FPGA using VHDL. The digital FIR filter of high throughput, low latency operating at above 1.3GHz was designed. An adaptive high capacity pipelined was introduced in the hybrid synchronous asynchronous design of the filter. The degree of the pipelining is dynamically variable depending upon the input. Concurrent execution of software or program can be achieved in FPGA through parallel processing. The designed digital FIR filter is simulated using ModelSim and implemented using Xilinx.

Provided by: International Journal of Computer Science Issues Topic: Hardware Date Added: Jul 2012 Format: PDF

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