The University of Maine at Machias
In this paper, the authors describe a router which is the key component of a scalable asynchronous on-chip and inter-chip communication infrastructure for an application-specific parallel computing system. The authors use this system as a universal platform for real time simulations of large-scale neural networks. The communications router supports multiple routing algorithms, and is pipelined to boost its throughput. The design considerations emphasize programmability and adaptive routing. Programmability offers a highly configurable architecture suited to a range of different applications.