A Programmable Timing Circuit with an Embedded BIST for Robust Timing of Sense Amplifiers

Provided by: AICIT
Topic: Storage
Format: PDF
A programmable timing circuit with an embedded BIST has been used in this paper for random-variation-tolerant timing of Static Random Access Memory (SRAM).In this scheme, a programmable replica-cell-based timing is used to tune the timing of Sense Amplifier Enable signal (SAE) by a control code determined by an at-speed BIST. This scheme has a low area overhead since it uses existing memory BIST circuit. Measurement results of 5 chips of a 16 K-bit SRAM in SMIC 65nm CMOS technology demonstrate that it can indeed track the timing under different process variations and maintain optimum yield and performance.

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