Due to scaling of MOS devices, SRAM read stability imposes a serious concern for future technology. The conventional 6T cell becomes more vulnerable to external noise due to voltage division between the access and the pull-down transistors in the inverter. This paper discusses the design and implementation of 11-T SRAM cell to improve the read stability and read power reduction. During read operation storage nodes are completely isolated from the bit lines. The average read power consumption reduces approximately 12% compared to the 6T cell due to lower discharging activity at read bitline and low leakage current.