A Quantitative Analysis of Performance Benefits of 3D Die Stacking on Mobile and Embedded SoC
3D stacked DRAM improves peak memory performance. However, its effective performance is often limited by the constraints of Row-to-Row activation Delay (tRRD), Four Active bank Window (tFAW), etc. In this paper, the authors present a quantitative analysis of the performance impact of such constraints. In order to resolve the problem, they propose balancing the budget of DRAM row activation across DRAM channels. In the proposed method, an inter-memory controller coordinator receives the current demand of row activation from memory controllers and re-distributes the budget to the memory controllers in order to improve DRAM performance. Experimental results show that sharing the budget of row activation between memory channels can give average 4.72% improvement in the utilization of 3D stacked DRAM.