A Quantitative Study of Memory System Interference in Chip Multiprocessor Architectures
The potential for destructive interference between running processes is increased as Chip Multi-Processors (CMPs) share more on-chip resources. The authors believe that understanding the nature of memory system interference is vital to achieve good fairness/complexity/performance trade-offs in CMPs. Their goal in this work is to quantify the latency penalties due to interference in all hardware-controlled, shared units (i.e. the on-chip interconnect, shared cache and memory bus). To achieve this, they simulate a wide variety of realistic CMP architectures.