Institute of Electrical & Electronic Engineers
In this paper, a novel coarse grained Reconfigurable Arithmetic Unit (RAU) is introduced. The RAU's design is based on a technique that inlines flexibility into custom Carry-Save-Arithmetic (CSA) circuits exploiting a stable and canonical interconnection scheme. The reconfigurable architecture prototype is presented. Two mapping strategies of DSP algorithms onto the proposed unit, are also analyzed. Experimental results report an average latency reduction of 32.63% and of 40% compared with datapath structured by primitive computational resources, using the first and the second mapping strategy respectively.