Institute of Electrical & Electronic Engineers
In this paper, the authors propose a generic frame for the implementation of a dual-core processor with two modes of operation. One is the safety mode that allows running the two cores in lock step in a classical master/checker fashion. A clock delay of 1.5 clock cycles between master and checker establishes the temporal redundancy to minimize the potential for common mode faults. The second operation mode allows a parallel execution of different instruction streams on the two cores in a multiprocessor fashion. The possibility to dynamically switch between the two modes allows for an efficient utilization of the duplicated core.