Provided by: Journal of Semiconductor Technology and Science (JSTS)
Date Added: Oct 2013
A reset-free anti-harmonic programmable Multiplying Delay-Locked Loop (MDLL) that provides flexible integer clock multiplication for high performance clocking applications is presented. The proposed MDLL removes harmonic locking problems by utilizing a simple harmonic lock detector and control logic, which allows this MDLL to change the input clock frequency and multiplication factor during operation without the use of start-up circuitry and external reset. A programmable Voltage Controlled Delay Line (VCDL) is utilized to achieve a wide operating frequency range from 80MHz to 1.2GHz with a multiplication factor of 4, 5, 8, 10, 16 and 20.