A Resilient Architecture for Low Latency Communication in Shared-L1 Processor Clusters

Provided by: edaa
Topic: Hardware
Format: PDF
A reliable and variation-tolerant architecture for shared-L1 processor clusters is proposed. The architecture uses a single-cycle mesh of tree as the interconnection network between processors and a unified Tightly Coupled Data Memory (TCDM). The proposed technique is able to compensate the effect of process variation on processor to memory paths. By adding one stage of controllable pipeline on the processor to memory paths the authors are able to switch between two modes: with and without pipeline. If there is no variation, the processor to memory path is fully combination and they have single-cycle read and write operations.

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