Large capacity Content Addressable Memory (CAM) is a key element in wide variety of applications. A major challenge in realization of such systems is the complexities of scaling MOS transistors. Converges of different technologies, which are well-matched with CMOS processing may allow extension of Moore’s law for a new year’s. This paper provides a new approach towards the design and modeling of Memristor-based CAM (MCAM) using a combination of MOS devices to form a core of a memory or logic cell that forms the building block of the CAM architecture.