International Journal of Engineering Trends and Technology
Universal Asynchronous Receive/Transmit (UART) has the objectives of firstly to satisfy specified testability requirements, and secondly to generate the lowest-cost with the highest performance implementation. UART has been an important input/output tool for decades and is still widely used. The additional BIST circuit that increases the hardware overhead increases designs time and size of the chip, which may degrade the performance. This paper focuses on the design of a UART chip with embedded BIST architecture using simple LFSR with the help of VHDL language.