A Scalable Low Power Issue Queue for Large Instruction Window Processors

Provided by: Association for Computing Machinery
Topic: Hardware
Format: PDF
Large instruction windows and issue queues are key to exploiting greater instruction level parallelism in out-of-order super-scalar processors. However, the cycle time and energy consumption of conventional large monolithic issue queues are high. Previous efforts to reduce cycle time segment the issue queue and pipeline wakeup. Unfortunately, this results in significant IPC loss. Other proposals which address energy efficiency issues by avoiding only the unnecessary tag-comparisons do not reduce broadcasts. These schemes also increase the issue latency.

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