A Self-Checking CMOS Full Adder in Double Pass Transistor Logic

Provided by: International Association of Engineers
Topic: Hardware
Format: PDF
In this paper, the authors present a self-checking implementation for adder schemes using the dual duplication code. To prove the efficiency of the proposed method, the circuit is simulated in double pass transistor CMOS at 32nm technology and some transient faults are voluntarily injected in the layout of the circuit. This fully differential implementation requires only 20 transistors which mean that the proposed design involves 28.57% saving in transistor count compared to the implementation using standard CMOS technology.

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