A Sense Amplifier Scheme with Offset Cancellation for Giga-Bit DRAM

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Provided by: Journal of Semiconductor Technology and Science (JSTS)
Topic: Hardware
Format: PDF
To improve low sense margin at low voltage, the authors propose a Negatively Driven Sensing (NDS) scheme and to solve the problem of WL-to-BL short leakage fail, a variable bit-line reference scheme with Free Level Pre-charged Bit-line (FLPB) scheme is adopted. The influence of the threshold voltage offset of NMOS and PMOS transistors in a latch type sense amplifier is very important factor these days. From evaluating the sense amplifier offset voltage distribution of NMOS and PMOS, it is well known that PMOS has larger distribution in threshold voltage variation than that of NMOS.
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