International Journal of Computer Applications
Aggressive scaling of device dimensions into ultra-short channel regime leads to significant process and intrinsic parameter fluctuations. A novel simulation algorithm capable of capturing statistical variability manifests in digital design is proposed. The only estimations for the algorithm inputs are the standard deviations of channel length and the gate voltage. Implementing the algorithm for the simulation of propagation delay times of the basic digital building blocks such as inverter, NAND2 and NOR2 circuits gives errors less than 7% against the most accurate results obtained from 'Atomistic' HSpice simulations.