A Six Transistors Full Adder
Using Multiple Valued Logic (MVL) have potential advantages in chips performing extensive arithmetic operations due to the reduction in the number of MOS transistors and relaxed wiring requirements due to the smaller word size. The MVL is a potential alternative to binary logic. A new six transistors multiple-valued current mode one bit full adder is presented. Simulations results utilizing standard 0.18 um CMOS technology illustrate a significant improvement in terms of number of transistors, chip area and propagation delay.