High resolution Analog-to-Digital Converters (ADCs) have been based on self-calibrated successive approximation technique. Unfortunately SAR technique requires N comparisons to convert N bit digital code from an analog sample. This makes SAR ADCs unsuitable for high speed applications. The authors' proposed technique reduces number of comparison requirements to N/4 for N bit conversion. This paper is the efficient circuit configuration for SAR ADC. A new circuit configuration which requires N/4 comparisons for N bit conversion is presented. This technique increases conversion speed by 75%.