Reliability is a growing concern in complex embedded systems. There is an increasing need to understand the failure modes and the overall reliability characteristics of large System-on-Chips (SoCs) which are built using IP components from diverse sources. IP providers must be able to specify the way silicon failures (e.g. single bit upsets, permanent faults) affect the operation of their IP components. This is especially challenging for providers of soft IP because the designs are often extremely configurable and the high-level failure mechanisms must be expressed independently of the underlying implementation technology.