A Statistical Traffic Model for On-Chip Interconnection Networks

Provided by: Princeton Software
Topic: Hardware
Format: PDF
Network traffic modeling is a critical first step towards understanding and unraveling network power/performance related issues. Extensive prior research in the area of classic networks such as the Internet, Ethernet, and wireless LANs transporting TCP/IP, HTTP, and FTP traffic among others, has demonstrated how traffic models and model-based synthetic traffic generators can facilitate understanding of traffic characteristics and drive early-stage simulation to explore a large network design space. Though on-chip networks (a.k.a Network-on-Chips (NoCs)) are becoming the de-facto scalable communication fabric in many-core System-on-Chips (SoCs) and Chip Multi-Processors (CMPs), no on-chip network traffic model that captures both spatial and temporal variations of traffic has been demonstrated yet.

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