A Structured Approach for Optimizing 4-Bit Carry-Lookahead Adder
In this paper, the authors present a comparative research of low-power and high-speed 4-bit full adder circuits. The representative adders used are a Ripple Carry Adder (RCA) and a Carry Look-ahead Adder (CLA). They also design a Proposed Carry Look-ahead Adder (PCLA) using a new method that uses NAND gate for modification which helps in reducing the Power Delay Product (PDP) for high performance applications. The layouts designed were simulated by HSpice based on 130nm CMOS technology at 1.2V supply voltages.