A Study and Analysis of High Speed Adders in Power-Constrained Environment

Provided by: International Journal of Soft Computing and Engineering (IJSCE)
Topic: Mobility
Format: PDF
An overview of the performance of 1-bit full adder in different CMOS logic styles and in depth examination of the advantages and limitations of each of them with respect of speed and power dissipation are presented. Ten 1-bit full adder circuit based on these logic styles are chosen for the extensive evaluation. These circuits were redesigned at the transistor-level in TSMC 0.18 m technology and comparison reported here uses Mentor Graphics ELDO simulations to assess their performance. The hybrid full adder exhibits not only the full swing logic and balanced outputs but also strong output drivability. The work presented in this paper gives a quantitative comparison of the adder cell performance.

Find By Topic