Georgia Institute of Technology
There has been little research that studies the effect of partitioning on parallel simulation of multicore systems. This paper presents their paper of this important problem in the context of null-message-based synchronization algorithm for parallel multicore simulation. This paper focuses on coarse grain parallel simulation where each core and its cache slices are modeled within a single Logical Process (LP) and different partitioning schemes are only applied to the interconnection network. In this paper the authors show that encapsulating the entire on-chip inter-connection network into a single logical process is an impediment to scalable simulation.