International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering (IJAREEIE)
Dynamic logic circuits are preferred for high speed applications. Wide OR gates are used in dynamic RAMs, static RAMs, high speed micro-processors and other high speed circuits. In spite of their high performance, dynamic logic circuit has high noise and extensive leakage which has caused problems for the circuits. To overcome these problems domino logic circuits are prefer which reduce noise immunity and sub-threshold leakage current in standby for wide OR gates. In this paper, the authors compare different domino logic design topologies for lowering the sub-threshold leakage current in standby mode, increasing the speed and increasing the noise immunity.