International Journal of Emerging Technology in Computer Science and Electronics ( IJETCSE)
The performance of trending technology in VLSI field supports ongoing expectation for high speed processing and lower area consumption. Since multiplier unit forms basic part of a processor, high speed multiplication becomes a requirement. Here, a novel architecture capable of performing high speed multiplication with the help of Vedic mathematics is discussed. Along with which 4:2 compressors and 7:2 compressors are used for the purpose of addition. When compared with existing methods, this type of multiplier using compressors is faster in performance.