A Survey on Systolic Array Multiplier and Its Implementation on FPGA

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Provided by: Creative Commons
Topic: Hardware
Format: PDF
The evolution of computer and Internet has brought demand for powerful and high speed data processing, but in such complex environment some methods can provide pristine solution. To handle above addressed situation, parallel computing is proposed as a solution to the contradiction. This paper reviews the implementation issues in systolic array multiplier for high speed data processing. This also introduces the concept of column compression and pipelining which improves the speed of execution. Multiplication is most commonly used operation in data processing.
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