A SW Performance Estimation Framework for Early System-Level-Design Using Fine-Grained Instrumentation

Provided by: edaa
Topic: Hardware
Format: PDF
The increasing demands of high-performance in embedded applications under shortening time-to-market has prompted system architects in recent time to opt for Multi-Processor Systems-on-Chip (MP-SoCs) employing several programmable devices. The programmable cores provide a high amount of flexibility and reusability, and can be optimized to the requirements of the application to deliver high-performance as well. Since application software forms the basis of such designs, the need to tune the underlying SoC architecture for extracting maximum performance from the software code has become imperative. In this paper, the authors propose a framework that enables software development, verification and evaluation from the very beginning of MP-SoC design cycle.

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