A Synthesis Postprocessor for Fully Morphable RTL Datapaths

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Provided by: National Technical University of Athens
Topic: Hardware
Format: PDF
Reconfigurable computing is intended to fill the gap between hardware and software, achieving potentially much higher performance than software, while maintaining a higher level of flexibility than hardware. In this paper, a special type of course grain reconfigurable RTL components, called morphable multipliers, are involved in high-level synthesis in the resulting FSMD architecture. Involvement is performed, starting with a minimal schedule, by splitting all conflicting control steps with a scheduling postprocessor. Following this approach, components that would remain idle in certain control steps are working full-time in two different modes, without any reconfiguration overhead applied to the critical path of the application.
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