A Synthesisable Quasi-Delay Insensitive Result Forwarding Unit for an Asynchronous Processor

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Provided by: The University of Maine at Machias
Topic: Data Centers
Format: PDF
The implementation of an efficient result forwarding unit for asynchronous processors faces the problem of the inherent lack of synchronization between result producer and consumer units. An efficient, full-custom solution to this problem has been proposed and implemented before (in the AMULET3 asynchronous processor) with the consequent limitations on design-space exploration and technology portability. The use of automatic synthesis to describe asynchronous systems is attractive in terms of rapid development, technology mapping transparency and design space exploration.
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