A Systematic Approach to Synthesis of Verification Test-Suites for Modular Soc Designs

Provided by: SERC
Topic: Hardware
Format: PDF
System-on-Chips (SoCs) are complex designs with heterogeneous modules (CPU, memory, etc.) integrated in them. Verification is one of the important stages in designing an SoC (System-on-Chips) that consumes upto 70% of the design time. In this paper, the authors present a methodology to automatically generate verification test-cases to verify a class of SoCs and also enable re-use of verification resources created from one SoC to another. A prototype implementation for generating the test-cases is also presented.

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