The contentious debates between RISC and CISC have died down, and a CISC ISA, the x86 continues to be popular. Now-a-days, processors with CISC-ISAs translate the CISC instructions into RISC style micro-operations (e.g.: uops of Intel and ROPS of AMD). The use of the uops (or ROPS) allows the use of RISC-style execution cores, and use of various micro-architectural techniques that can be easily implemented in RISC cores. This can easily allow CISC processors to approach RISC performance. However, CISC ISAs do have the additional burden of translating instructions to micro-operations.