High resolution Analog-to-Digital Converters (ADCs) have been based on self-calibrated Successive AppRoximation (SAR) technique. Unfortunately SAR technique requires N comparisons to convert N bit digital code from an analog sample. This makes SAR ADCs unsuitable for high speed applications. The authors' proposed technique reduces number of comparison requirements to N/2 for N bit conversion. The main features of this paper are the efficient circuit configuration for SAR ADC. A new circuit configuration which requires N/2 comparisons for N bit conversion is presented.