A Time-Power Efficient Decimator Using Vedic Algorithm

An oversampling ADC requires a decimation filter to reduce the rate of samples for the succeeding stages running at slower rates. The power consumption and speed of a successive-approximation ADC predominately depends on the power sopped up by decimator and its speed. This necessitates a need to design a low power and high speed decimation filter to improve the overall system performance. A new algorithm based on ancient Indian mathematics is applied for the design of decimator to serve this purpose.

Provided by: Dr.B.R Ambedkar National Institute of Technology Topic: Hardware Date Added: Sep 2010 Format: PDF

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