A Timing Model of Sequential Circuits for Efficient Standard Cell Library Characterization

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Provided by: Research and Educational Society
Topic: Hardware
Format: PDF
Accurate estimation of delay in a circuit is a critical task in deep sub-micron technology due to Process, Voltage and Temperature (PVT) variation. Look-Up Table (LUT) based delay estimation method is the most widely used in Static Timing Analysis (STA). In this method, delay is obtained at some load capacitance Cl and input transition time (trin) values using spice simulations and is estimated using linear interpolation at other values of Cl and trin. The timing parameters of a latch (setup time, hold time, etc.) are expressed similarly in the LUT as a function of input transition, load capacitance and clock skew.
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