Provided by: National University of Singapore
Date Added: Oct 2011
With the advent of multi-core architectures, Worst Case Execution Time (WCET) analysis has become an increasingly difficult problem. In this paper, the authors propose a unified WCET analysis framework for multi-core processors featuring both shared cache and shared bus. Compared to other previous papers, their paper differs by modeling the interaction of shared cache and shared bus with other basic micro-architectural components (e.g. pipeline and branch predictor). In addition, their framework does not assume a timing anomaly free multicore architecture for computing the WCET.