Institute of Electrical & Electronic Engineers
In this paper, the authors propose tightly-coupled, multi-core cluster architecture with shared, variation-tolerant, and accuracy-reconfigurable Floating-Point Units (FPUs). The resilient shared-FPUs dynamically characterize FP pipeline Vulnerability (FPV) and expose it as metadata to a software scheduler for reducing the cost of error correction. To further reduce this cost, their programming and runtime environment also supports controlled approximate computation through a combination of design time and runtime techniques. They provide OpenMP extensions (as custom directives) for FP computations to specify parts of a program that can be executed approximately.