A Versatile, Low Latency HyperTransport Core
In this paper, the authors present the design of a generic HyperTransport (HT) core. It is specially optimized to achieve a very low latency. The core has been verified in system using the rapid prototyping methodology with FPGAs. This exhaustive verification and the generic design allow the mapping to both ASICs and FPGAs. The implementation described in this paper supports a link width of 16bit, as is used in Opteron based systems. On a Xilinx Virtex4FX60, the core supports a link frequency of 400MHz DDR and offers a maximum bidirectional bandwidth of 3.6 GB/s.