The design of high-speed and low-power VLSI architectures needs efficient processing units, which are optimized for the speed and power consumption. An INCrementer/DECrementer (INC/DEC) is an important building block in many digital systems such as the address generation unit of microcontrollers and microprocessors. In this paper, the authors propose novel architectures and designs for very fast and low power INC/DEC circuits that can be used in Low power RISC processors. The designs operate on the 2N-2N2P energy recovery logic design approach. The 350nm technology library files from AMS350nm standard CMOS technology are used in the paper.