Delft University of Technology
In this paper, the authors present a Very Long Instruction Word (VLIW) softcore processor implemented in an FPGA. The processor Instruction Set Architecture (ISA) is based on the VEX ISA. The issue-width of the processor can be dynamically adjusted. The processor has two 2-issue cores, which can be run independently. If not in use, each core can be taken to a lower power mode by gating off the source clock. The two 2- issue cores can be combined at run-time to form one larger 4-issue core.