A VLSI Implementation of Modulo Multiplier by using Radix-8 Modified Booth Algorithm

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Provided by: International Journal of Innovative Technology and Exploring Engineering (IJITEE)
Topic: Hardware
Format: PDF
Special moduli set Residue Number System (RNS) of high Dynamic Range (DR) can speed up the execution of very large word-length repetitive multiplications found in applications like public key cryptography. The modulo 2n-1multiplier is usually the noncritical data path among all modulo multipliers in such high-DR RNS multiplier. This timing slack can be exploited to reduce the system area and power consumption without compromising the system performance. With this precept, a family of radix-8 booth encoded modulo 2n-1 multipliers, with delay adaptable to the RNS multiplier delay, is proposed.
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