Abstract State Machines as an Intermediate Representation for High-Level Synthesis

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Provided by: edaa
Topic: Hardware
Format: PDF
This paper presents a high-level synthesis methodology that uses the Abstract State Machines (ASMs) formalism as an Intermediate Representation (IR). The authors perform scheduling and allocation on this IR, and generate synthesizable VHDL. They have the following advantages when using ASMs as an IR: it allows the specification of both sequential and parallel computation, it supports an extension of a clean timing model based on an interpretation of the sequential semantics, and it has well-defined formal semantics, which allows the integration of formal methods into the methodology. While they specify their designs using ASMs, they do not mandate this.
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