Provided by: edaa
Date Added: Jun 2009
FPGAs are widely used for evaluating the error-floor performance of LDPC (Low-Density Parity-Check) codes. The authors propose a scalable vector decoder for FPGA-based implementation of Quasi-Cyclic (QC) LDPC codes that takes advantage of the high bandwidth of the embedded memory blocks (called Block RAMs in a Xilinx FPGA) by packing multiple messages into the same word. They describe a vectorized overlapped message passing algorithm that results in 3.5X to 5.5X speedup over state-of-the-art FPGA implementations in literature.