ACCESS: Smart Scheduling for Asymmetric Cache CMPs

Provided by: Pennsylvania State Employees Credit Union
Topic: Hardware
Format: PDF
In current, Chip Multi-Processors (CMPs), a significant portion of the die is consumed by the last-level cache. Until recently, the balance of cache and core space has been primarily guided by the needs of single applications. However, as multiple applications or Virtual Machines (VMs) are consolidated on such a platform, researchers have observed that not all VMs or applications require significant amount of cache space. In order to take advantage of this phenomenon, the authors explore the use of asymmetric last-level caches in a CMP platform.

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