International Journal of Computer Applications in Engineering Sciences (IJCAES)
In a BIST design, the generation and application of the test vectors and the analysis of the resulting response are part of the circuit (or system) under test. Weighted pseudorandom Built-In Self-Test (BIST) schemes have been used to reduce the number of test vectors for achieving complete fault coverage in BIST applications. 3-weight pattern generation uses only three weights, 0, 0.5 and 1. An accumulator-based 3-weight test pattern generation scheme is presented that tests the MAC unit with different multiplier such as Vedic multiplier, booth multiplier, array multiplier and different adders such as carry look ahead adder and ripple carry adder.