The International Journals of Engineering & Sciences (IJENS)
As the demand for faster circuitry increases, the transistors size decreases in order to achieve needed speeds. In this paper, an enhancement to previous semi-analytical models of the gate extrinsic capacitance of FinFET transistors is introduced. This allows to properly model the capacitance behavior when multi-Fins are used. The proposed semi-analytical models take into account the source/drain electrode and contact areas. In this paper, it is shown that this modification reduced the modeling error to only 3%.