Institute of Electrical & Electronic Engineers
As industry moves towards multicore chips, Network-on-Chips (NoCs) are emerging as the scalable fabric for interconnecting the cores. With power now the first-order design constraint, early-stage estimation of NoC power, performance, and area has become crucially important. In this paper, the authors develop a accurate architecture-level on-chip router cost models using machine-learning-based regression techniques. Compared against existing models (e.g., ORION 2.0 and parametric models), their models reduce estimation error by up to 89% on average.