Massachusetts Institute of Technology
Inclusive caches are commonly used by processors to simplify cache coherence. However, the trade-off has been lower performance compared to non-inclusive and exclusive caches. Contrary to conventional wisdom, the authors show that the limited performance of inclusive caches is mostly due to inclusion victims - lines that are evicted from the core caches to satisfy the inclusion property - and not the reduced cache capacity of the hierarchy due to the duplication of data. These inclusion victims are incorrectly chosen for replacement because the Last-Level Cache (LLC) is unaware of the temporal locality of lines in the core caches.