Adaptive Cache Management for a Combined SRAM and DRAM Cache Hierarchy for Multi-Cores

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Provided by: edaa
Topic: Storage
Format: PDF
The \"Memory bandwidth\" problem refers to the significantly increasing gap between the performance of a processor to process data and the performance to fetch the data it needs. Memory bandwidth has become a major performance bottleneck for memory intensive applications with large working set sizes. A recent trend towards mitigating the Memory Bandwidth problem is to use a large on-chip DRAM Last-Level-Cache (LLC). For example, IBM POWER7 utilizes a 32 MB shared LLC cache using embedded DRAM technology to reduce the off-chip accesses.
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