Adaptive Cluster Throttling: Improving High-Load Performance in Bufferless On-Chip Networks

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Provided by: Carnegie Mellon University
Topic: Hardware
Format: PDF
Higher core counts and increasing focus on energy efficiency in modern Chip Multi-Processors (CMP) have led to renewed interest in simple and energy-efficient Network-on-Chip (NoC) designs. Several recent proposed designs trade off network capacity for efficiency, based on the observation that traditional networks are overprovisioned for many workloads. Bufferless routing is one such example. However, when the application workload requires high interconnect performance, the inefficiencies of bufferless interconnects can cause significant performance degradations. Previous work has tackled various issues with bufferless routing, but little work has been done to improve performance at high network load.
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